# How to design a sequential circuit

## Is flip flop a synchronous or an asynchronous sequential circuit?

The edge-triggered D-flip-flop is an asynchronous circuit. You can see one of the following implementations. I like this one because you can analyze it, simulate it, and even build it with standard gates. In addition, you can see where typical parameters for edge triggered circuits such as setup and hold times come from. It's essentially 3 SR latches that are tied together in a certain way.

Let's walk this through a set of {inputs, outputs}. Then you can analyze it for others.

Let's say CLK = 0, D = 0 at power up. Also assume QB = 1, Q = 0. It is also likely to appear as QB = 0, Q = 1. You can imagine adding a reset in this circuit.

As CLK = 0 and D = 0 you get {O1, O2, O3, O4} as {0, 1, 1, 1}. Since O2 and O3 are each 1, QB and Q remain stable, in this case as 1 and 0.

Now suppose D makes the transition 0-> 1. This changes {O1, O2, O3, O4} to {1, 1, 1, 0}. Still no effect on QB, Q.

This transition must go through G4 and G1 in order to propagate to one of the entrances of G2. This defines the setup time as (delay (G1) + delay (G4))

Now let CLK pass from 0-> 1. If you analyze all the inputs for G1, G2, G3, and G4, you can see that {O1, O2, O3, O4} changes to {1, 0, 1, 0}. This will spread to QB and Q and make them QB = 0, Q = 1.

The D input must be held at a stable value for a delay equal to the delay (G2) after the CLK transition. This is waiting time.

You can verify that after this delay, when D changes, there is no effect on the output. There is also no effect on the output when CLK transitions from 1-> 0.

simulate this circuit - scheme created with CircuitLab

This comes from one of the older textbooks, "Logic Circuit Design" by Prof. D. Zissos.