What is a master slave flip flop

Master-slave flip-flop

All two-edge-controlled flip-flops are master-slave flip-flops. They react to the positive as well as to the negative clock edge.

The data pending at the input are read in on the positive clock edge. The data is output with a delay on the negative clock edge.

Circuit principle using the example of a JK-MS-FF


The JK-MS flip-flop consists of two individual JK flip-flops that are directly connected to each other. The outputs of the first, the master flip-flop, are connected to the inputs of the second, the slave flip-flop.
The first flip-flop reacts to the rising clock edge. The second flip-flop on the falling clock edge.
So that the slave flip-flop reacts to the falling edge, the clock input is negated with a NOT operation.

Pulse diagram


In the pulse diagram, C denotes the clock signal. J and K are the two inputs and Q the output.
The flip-flop status is read in with the positive clock edge. The status is passed on to the output with the negative clock edge.

Circuit symbols

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